Integrated circuits (“ICs”) are incorporated into many electronic devices. IC packaging has evolved, such that multiple ICs may be vertically stacked in so-called three-dimensional (“3D”) packages in order to save horizontal area on a printed circuit board (“PCB”). An alternative packaging technique, referred to as a 2.5D package may use an interposer, which may be formed from a semiconductor material such as silicon, for coupling one or more dies to a PCB. A plurality of IC chips, which may be of heterogeneous technologies, are mounted on the interposer. The packaging industry is also considering combinations of the two techniques, in which a stack of dies are mounted on an interposer, along with other dies or other stacks of dies. Both 2.5D and 3D IC packaging include forming interconnections between the various ports in plural dies.
Integration of plural dies into a package poses many challenges. Individually, each system on a chip (SoC) is tested, and may have many Known Good Functions (IPs). The SoC works as one complete unit. As such, it is verified as a complete unit including the interconnect among Known Good IPs. On the other hand, the 3D IC stack includes Known Good Dies (KGD). Each die is individually verified to be functionally correct.
The verified dies are then integrated into the stacked package configuration. Both 2.5D and 3D IC inter-die connectivity involve the addition of a huge number of microbumps (μbumps) connected between dies.
Debugging stacked dies is very tedious, time consuming and error prone. If an error is made during the debugging process it may become necessary to respin the stacked dies.